1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same, particularly to a semiconductor device having a via hole and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, a lower conductor (a wiring layer formed on a substrate or a diffusion layer) and an upper conductor corresponding thereto are electrically connected by providing an opening (hereafter, referred to as a via hole) reaching the lower conductor in a semiconductor substrate or an insulation film deposited on a surface of a semiconductor substrate and providing metal (copper, aluminum or tungsten) as a wiring in this via hole. The via hole is also called a through hole or a contact hole.
An example of a conventional method of manufacturing a semiconductor device having such a via hole will be described referring to figures. FIGS. 14 to 16 are schematic cross-sectional views showing the manufacturing process in due order.
As shown in FIG. 14, a semiconductor substrate 100 made of silicon or the like is prepared. A pad electrode 101 as a lower conductor is provided on the front surface of the semiconductor substrate 100. Then, a via hole 102 is formed by etching so as to penetrate the semiconductor substrate 100 from the front surface to the back surface and expose the pad electrode 101. A first insulation film (e.g. a silicon oxide film) 103 covering the front surface of the semiconductor substrate 100 and a passivation film (e.g. a silicon nitride film) 104 covering the pad electrode 101 at least partially are formed. A glass substrate 106 as a supporting body is attached on the front surface of the semiconductor substrate 100 with an adhesive layer 105 made of epoxy resin or the like interposed therebetween.
Then, a second insulation film 107 (e.g. a silicon oxide film or a silicon nitride film) is formed on the back surface of the semiconductor substrate 100 including in the via hole 102 by, for example, a CVD method. Then, the second insulation film 107 on the bottom of the via hole 102 is removed by etching to expose a part of the pad electrode 101.
Then, as shown in FIG. 15, a barrier layer 108 is formed in the via hole 102. This barrier layer 108 preferably has low resistance and is made of a titanium (Ti) layer or a titanium nitride (TiN) layer, for example.
While the CVD method (the chemical vapor deposition method) is one of methods of forming the barrier layer 108, there is a strong possibility that an impurity is mixed in the film by the CVD method to cause degradation of film quality such as reduction of conductivity. Furthermore, the CVD method also has problems that the running cost of its device itself and a material is significantly high and the process is unstable.
Therefore, it is preferable to use a sputtering method for forming the barrier layer 108 since it is simpler and more stable and provides the lower running cost and less possibility of the film quality degradation than the CVD method.
However, since the sputtering method sometimes forms a film insufficiently covering the sidewall and bottom (particularly, a corner portion) of the via hole 102, the film deposition by the sputtering method need be performed enough as shown in FIG. 15 in order to address this problem. Therefore, it is inevitable that the barrier layer 108 on the back surface of the substrate and the bottom of the via hole 102 is thickened.
Alternatively, the coverage of the barrier layer 108 on the bottom and sidewall of the via hole 102 is enhanced by performing reverse-sputtering (etching) to the barrier layer 108 formed by the sputtering method first to scatter the barrier layer 108 deposited on the bottom of the via hole 102 therearound (e.g. Japanese Patent Application Publication No. H6-302543) as shown in FIG. 16.
As described above, the barrier layer 108 is formed by the sputtering or the combination of the sputtering and the reverse-sputtering. Those techniques are described in Japanese Patent Application Publication Nos. H6-302543, 2002-118109 and 2001-524753.
However, when the sputtering is performed to excess, while the coverage of the barrier layer is enhanced, the barrier layer on the bottom of the via hole is formed too thick as shown in FIG. 15, thereby causing a problem that the resistance of an electrode formed in the via hole (hereafter, referred to as via resistance) is increased.
Furthermore, when the barrier layer is formed by the reverse-sputtering after the sputtering, the barrier layer on the bottom of the via hole has a thickness X (see FIG. 16) that is obtained by subtracting the thickness of the film removed by the reverse-sputtering (etching) from the thickness of the film formed by the sputtering method first. By this method, it is difficult to accurately control the thickness X of the ultimate barrier layer on the bottom of the via hole and the via resistance is not properly controlled.
The invention is directed to a semiconductor device and a method of manufacturing the same that achieve both the prevention of the barrier layer insufficiently covering the via hole and the control of the via resistance at the same time.